The present invention relates to techniques for improving accuracy in charge transfer devices, especially those which use multiple pipelined stages.
Charge transfer devices, including but not limited to Charge Coupled Devices (CCDs), have long been used to implement important functions such as analog to digital conversion (ADC) and digital to analog conversion (DAC) in electronic systems. For example, ADCs and DACs are now an essential part of numerous consumer electronic devices, such as digital cameras, cellular telephones, wireless networking equipment, audio devices such as MP3 players, and video equipment such as Digital Video Disk (DVD) players, High Definition Digital Television (HDTV) equipment, and other products.
There are several ways to implement CCD based converters. One way is described in U.S. Pat. No. 4,375,059 issued to Schlig, which is an early example of a successive approximation, Charge Coupled Device (CCD) based ADC. In that design, a set of charge storage stages is arranged as a serial pipeline register. An input source charge passes from stage to stage down the pipeline. A reference charge generator and a charge splitter at each stage generate reference signals. A first of the reference signals is compared to the source charge that is temporarily stored at the corresponding stage. The comparison generates a binary one, if the source charge is greater than or equal to the first reference charge, or a binary zero, if the source charge is less than the first reference charge. If a binary one is generated, only the stored contents of the stage are passed through to the next successive stage. However, if a binary zero is generated, the stored contents of the stage are passed to a next successive stage, together with a second reference charge, in such a way that the two charges are combined. Auxiliary buffer registers are provided to temporarily store the output bits of the comparators. The buffer registers thus provide a digital output word for each input source charge packet.
A further refinement in CCD-based converter design is found in U.S. Pat. No. 5,579,007 issued to Paul. In that arrangement, the successive approximation pipeline is arranged to handle a serial stream of both positive and negative differential signal charges corresponding to a differential version of the input signal. The differential signal structure provides improved sensitivity in the charge to voltage translation process, and thus increased dynamic range. The structure also exhibits reduce sensitivity to mismatches, by suppression of common mode noise signals in the charge domain.
In order to provide high precision, even the differential successive approximation type CCD converter must often be trimmed or actively calibrated. The precision of the calibration apparatus must therefore be considerably better than the converter itself, making its design quite challenging. These techniques usually require precise, low noise, low DC-offset amplifiers and/or comparators. Unfortunately, thermal noise, low frequency (l/f) noise, and DC voltage offsets produced by these devices still provide limits on the accuracy of the converter.